Wednesday, March 11, 2015

Xilinx moves programmable chip design to system-level

Read the article on Electronics Weekly

http://www.electronicsweekly.com/news/products/fpga-pld/xilinx-moves-programmable-chip-design-system-level-2015-03/
Xilinx moves programmable chip design to system-leve - See more at: http://www.electronicsweekly.com/news/products/fpga-pld/xilinx-moves-programmable-chip-design-system-level-2015-03/#sthash.KVvw9Ian.dpuf
Xilinx continues to introduce FPGA development tools which it expects will make design of programmable devices accessible to a range of non-specialist developers.
The SDSoC for the company’s Zynq All Programmable SoCs and MPSoCs is configured to simplify device programming by using an Eclipse integrated design environment (IDE).
The intention is to support system-level design and the tool has a C/C++ full-system optimising compiler, automated SW acceleration in programmable logic and automated system-level interconnect generation.
The compiler targets both the Zynq’s ARM processors and the programmable logic.
The Eclipse IDE with C/C++ runs on bare metal or operating systems such as Linux and FreeRTOS as its input.
According to Giles Peckham, European marketing manager, Xilinx, the tool enables the creation of “complete heterogeneous multi-processing systems, including reuse of legacy HDL IP Blocks as C-callable libraries”.
“Unlike traditional separate hardware-centric and software-centric flows, which can result in development delays and uncertainty in system architecture and performance, SDSoC is architected to provide rapid system profiling, SW acceleration in programmable logic, and system architecture exploration in a familiar framework,” said Peckham.
SDSoC provides board support packages for Zynq All Programmable SoC-based development boards including the ZC702, ZC706, as well as third party and market specific platforms including the Zedboard, MicroZed, ZYBO, and Video and Imaging development kits.
- See more at: http://www.electronicsweekly.com/news/products/fpga-pld/xilinx-moves-programmable-chip-design-system-level-2015-03/#sthash.KVvw9Ian.dpuf
Xilinx continues to introduce FPGA development tools which it expects will make design of programmable devices accessible to a range of non-specialist developers.
The SDSoC for the company’s Zynq All Programmable SoCs and MPSoCs is configured to simplify device programming by using an Eclipse integrated design environment (IDE).
The intention is to support system-level design and the tool has a C/C++ full-system optimising compiler, automated SW acceleration in programmable logic and automated system-level interconnect generation.
The compiler targets both the Zynq’s ARM processors and the programmable logic.
The Eclipse IDE with C/C++ runs on bare metal or operating systems such as Linux and FreeRTOS as its input.
According to Giles Peckham, European marketing manager, Xilinx, the tool enables the creation of “complete heterogeneous multi-processing systems, including reuse of legacy HDL IP Blocks as C-callable libraries”.
“Unlike traditional separate hardware-centric and software-centric flows, which can result in development delays and uncertainty in system architecture and performance, SDSoC is architected to provide rapid system profiling, SW acceleration in programmable logic, and system architecture exploration in a familiar framework,” said Peckham.
SDSoC provides board support packages for Zynq All Programmable SoC-based development boards including the ZC702, ZC706, as well as third party and market specific platforms including the Zedboard, MicroZed, ZYBO, and Video and Imaging development kits.
- See more at: http://www.electronicsweekly.com/news/products/fpga-pld/xilinx-moves-programmable-chip-design-system-level-2015-03/#sthash.KVvw9Ian.dpuf

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