Samsung Targets 4nm in 2020

SAN FRANCISCO—Samsung Electronics Co. Ltd. Wednesday (May 24) updated its foundry technology roadmap, including detailing its second-generation FD-SOI platform, several bulk silicon FinFET processes down to 5nm and a 4nm “post FinFET” structure process set to be in risk production in 2020.

Samsung, which formally broke its foundry operation into a separate business unit called Samsung Foundry last week, also reiterated previously announced plans to put extreme ultraviolet (EUV) lithography into production in 2018 at the 7nm node.
”We are extremely aggressive with our roadmap, not only in planning, but in announcing what we are going to be doing in the next three to four years,” said Kelvin Low, senior director of foundry marketing at Samsung, in an interview in advance of Wednesday’s announcement.
The most forward-looking of Samsung’s Wednesday announcements, which were unveiled at the company’s annual U.S. foundry technology forum in Santa Clara, Calif., is the company’s proprietary next-generation device architecture, which it calls multi-bridge channel FET (MBCFET). The structure is described as Samsung’s own proprietary flavor of gate-all-around FET (GAAFET) technology that uses a nanosheet device to overcome the physical scaling and performance limitations of the FinFET architecture.
Samsung’s roadmap calls for putting MBCFET technology into risk production in 2020 in its 4nm low-power plus (LPP) process.
Between now and 2020, Samsung plans to put in production an 8nm LPP process this year, a 7nm LPP process featuring EUV next year and 5nm and 6nm LPP processes in 2019.
EUV, a long-promised an often pushed out lithography technology to succeed 193nm immersion lithography, finally appears to be on the verge of being inserted into production. Taiwan Semiconductor Manufacturing Co. (TSMC) and Globalfoundries, Samsung’s chief foundry competitors, have both declared their intentions to use EUV in production in 2019.
Samsung has demonstrated the EUV power source production target of 250W in process development. According to Low, the “magic number” for productivity with EUV is 1,500 wafers per day. Samsung has already exceeded 1,000 wafers per day and has a high degree of confidence that 1,500 wafers per day is achievable, Low said.

“We are confident that we are ready to bring [EUV] into production in 2018,” Low said. “This is no longer a concept roadmap item.”
Low said that Samsung, unlike some competitors, sees the 10nm node as a “long-lead node” that will provide customers with the performance and desired power consumption on leading edge designs for a considerable period of time.
“As long as we are able to deliver power, performance and scaling in production, we think it will be a very productive node,” Low said.
Samsung also detailed an 18nm FD-SOI process technology targeted for risk production in 2019. The company plans to gradually expand its current 28nm FD-SOI process into a broader platform by incorporating RF and embedded MRAM options before offering its second-generation FD-SOI platform, which it says will offer a 40 percent power savings, a 20 percent performance improvement and area advantages over its predecessor.

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