Chip-Making Process Packs More onto Wafer Space

Computer chip makers constantly strive to pack more transistors into less space, but the barrier is always the size of the wafer itself and the physical limitations of the transistors.

Now, taking advantage of a germanium wafer coated with a layer of graphene, a team of engineers from the University of Wisconsin–Madison and the University of Chicago has devised a simpler, reproducible and less expensive manufacturing approach using directed self-assembly.
hemical patterns consisting of alternating graphene and germanium stripes (left side) are used to direct the self-assembly of block co-polymers into well-ordered patterns (right side). The top images are schematics, and the bottom images are scanning electron micrographs. The scale bars are 200 nm. Source: University of Wisconsin-Madison
Directed self-assembly is a large-scale, nano-patterning technique that can increase the density of circuit patterns and circumvent some limitations of conventional lithographic processes for printing circuits on wafers of semiconductors such as silicon. The technique, which enables the fabrication of intricate, precisely ordered polymer patterns for circuitry, is being adopted and developed by electronics manufacturers to address the ever-smaller requirements of future devices.
The researchers’ new method is fast and requires only two steps: lithography and plasma etching.
As explained by researchers, in the first demonstration of their technique, they used electron beam lithography and a mild plasma etching technique to pattern one-atom-thick graphene stripes on a germanium wafer. Then they spin-coated the wafer with a common block co-polymer called polystyrene-block-poly(methyl methacrylate).
When heated, the block co-polymer completely self-assembled in just 10 minutes compared to 30 minutes using conventional chemical patterns, and had fewer defects. The researchers attribute this rapid assembly to the smooth, rigid and crystalline surfaces of germanium and graphene.

While the stripe pattern was a simple demonstration of the technique, researchers also showed it works with more architecturally complex or irregular patterns, including those with 90° bends.

“These templates offer an exciting alternative to traditional chemical patterns composed of polymer mats and brushes, as they provide faster assembly kinetics and broaden the processing window, while also offering an inert, mechanically and chemically robust, and uniform template with well-defined and sharp material interfaces,” said Paul Nealey, a University of Chicago chemical engineer.
Scanning electron micrographs of block co-polymer films assembled on graphene/germanium chemical patterns with 90° bends (left side) and with density multiplication by a factor of 10 (right side). The black dotted lines (right side) indicate the period of the graphene/germanium chemical pattern, in which the period of the assembled block co-polymer is reduced by a factor of 10 due to density multiplication. The scale bars are 200 nm. Source: University of Wisconsin-Madison Their technique combines the uniformity and simpler processing of traditional “top-down” lithographic methods with the advantages of “bottom-up” assembly and greater density multiplication, and offers a promising route for large-scale production at significantly reduced cost, the researchers said.

“Using this one-atom-thick graphene template has never been done before. It’s a new template to guide the self-assembly of the polymers,” said Zhenqiang “Jack” Ma, an electrical engineer at UW–Madison. “This is mass-production compatible. We opened the door to even smaller features.”

http://electronics360.globalspec.com/article/7327/chip-making-process-packs-more-onto-wafer-space