U.S. Spurs Industrial Chip Market Growth

SAN FRANCISCO—The industrial semiconductor market is expected to grow at a compound annual growth rate (CAGR) of 8% between 2014 and 2019, when it is projected to be worth $59.5 billion, according to a forecast from market research firm IHS Inc.

IHS (Englewood, Colo.) predicts that increased capital spending and continued economic growth, especially in the U.S., will spur demand for industrial semiconductors. The firm lists commercial aircraft, LED lighting, digital video surveillance, climate control, traction and medical devices as the drivers for most of the global demand for industrial ICs.
IHS estimates that the United States remains the largest market for industrial semiconductors, accounting for 30% of all chips used in industrial applications in 2015. China was the second largest industrial IC market, accounting for 16% of the global total, according to IHS.

Robbie Galoso, IHS

“Robust economic growth and increased capital spending in the United States is good news for industrial semiconductor suppliers, because they have the world’s largest industrial equipment makers, including General Electric, United Technologies and Boeing,” said Robbie Galoso, associate director for industrial semiconductors at IHS Technology, in a statement. “Strong industrial equipment demand will further boost sales of optical semiconductors, analog chips and discretes, which are the three largest industrial semiconductor product segments.”
LED lighting is expected to be the largest driver of industrial semiconductor growth. The LED market is forecast to be worth $14.5 billion in 2019, thanks to a boom in global LED lighting, IHS said.

Click here for larger image

The microcontroller market is expected to grow from $4.4 billion in 2014 to $6.3 billion in 2019, thanks largely to advances in power efficiency and integration, IHS said.
IHS projects that analog application-specific ICs will grow strongly through 2019, reaching $4.7 billion in industrial markets, especially in factory automation, power and energy and lighting. IHS expects growth to come primarily from power management products and device integration from firms such as Texas Instruments Inc., Analog Devices Inc., NXP Semiconductors NV and others.
The market for discrete power transistors, thyristors, rectifiers and power diodes is expected to grow to $7.8 billion in 2019, due to the policy shift toward energy efficiency in the factory automation market, IHS said.

http://www.eetimes.com/document.asp?doc_id=1329272

Moore's Law Stutters at Intel

Intel has announced that it’s moving away from its current “tick-tock” chip production cycle and instead shifting to a three-step development process that will “lengthen the amount of time [available to] utilize... process technologies.”

For years now, Intel has run its chip business on a ‘tick-tock’ basis: First it develops a new manufacturing technique in one product cycle (tick!), then it upgrades its microprocessors in the next (tock!).
But recently it’s been struggling to keep pace. The last advance in Intel’s chips was to move to a design created using 14 nanometer transistors aboard its Broadwell processors, which given the tick-tock cycle we’d expect to be miniaturized in 2016. But last year Intel was forced to announce that its 2016 chip line-up, called Kaby Lake, would continue to use 14 nanometer processes. Instead, the next shrinkage would arrive in the second half of 2017, when Intel said it would shift to transistors that measure just 10 nanometers in its Cannonlake chips.

Now, in an annual report filing, Intel has officially announced that it’s moving away from the tick-tock timing. Instead, it will run on a three-step development process that it refers to as “Process-Architecture-Optimization.” From the filing:

As part of our R&D efforts, we plan to introduce a new Intel Core microarchitecture for desktops, notebooks (including Ultrabook devices and 2 in 1 systems), and Intel Xeon processors on a regular cadence. We expect to lengthen the amount of time we will utilize our 14nm and our next generation 10nm process technologies, further optimizing our products and process technologies while meeting the yearly market cadence for product introductions.

While it doesn’t explicitly refer to timescales, the news suggests that Moore’s Law—which states that the number of transistors on an integrated circuit doubles every two years—is stuttering at Intel. The size of the transistor, of course, dictates the number you can squeeze onto a chip. Indeed, last summer Intel’s CEO Brian Krzanich mused that “the last two technology transitions have signaled that our cadence today is closer to 2.5 years than two.”
All of this is, of course, the result of the original “tick” becoming increasingly difficult to bring about: The limit of what can be done with conventional silicon is fast being approached. IBM has announced that it can create 7-nanometer transistors, but it’s a new technique using silicon-germanium in the manufacturing process rather than pure silicon, and at any rate the process is a way off being fully commericialized.
The truth is that we may just have to start waiting a little longer for faster silicon, for now at least.

http://gizmodo.com/moores-law-stutters-as-intel-switches-from-2-step-to-3-1766574361

Google Seeks To Sell Prominent Robot Maker Boston Dynamics

oogle's parent company is reportedly shopping a high-profile robotics subsidiary after just more than two years.
Bloomberg, citing two people familiar with Alphabet's plans, indicated that company officials determined that Boston Dynamics was unlikely to generate revenue in coming years — a key emphasis of the tech giant’s research strategy — and decided to cut it loose.

Boston Dynamics was one of several robotics acquisitions by Google in recent years. The subsidiary generated significant buzz with online videos, including footage of a robot dog training with the Marines and of researchers effectively beating up their latest humanoid robot.
The division, however, reportedly struggled to find proper leadership and repeatedly clashed with officials from Replicant, Google's robotics initiative.

(Image credit: Boston Dynamics)

Boston Dynamics subsequently wasn't rolled into the Google X innovation arm, and Google X officials expressed particularly discomfort about the humanoid video last month.
Bloomberg reported that Toyota's research arm and Amazon.com could be possible destinations for the company.

http://www.manufacturing.net/news/2016/03/google-seeks-sell-prominent-robot-maker-boston-dynamics?et_cid=5190680&et_rid=490548696&location=top&et_cid=5190680&et_rid=490548696&linkid=http%3a%2f%2fwww.manufacturing.net%2fnews%2f2016%2f03%2fgoogle-seeks-sell-prominent-robot-maker-boston-dynamics%3fet_cid%3d5190680%26et_rid%3d%%subscriberid%%%26location%3dtop

The Microchip That Made Silicon Valley—and All Modern Technology—Possible

All modern technology comes down to one tiny piece of oxidized silicon cemented atop a circuit. Without the pioneers who created it, future founding fathers such as Bill Gates and Mark Zuckerberg would have had nothing upon which to build their empires. Newsweek explores the phenomenon of the microchip in this article excerpted from a new Special Edition, The Founding Fathers of Silicon Valley, Exploring 60 Years of Innovation, by Issue Editor Alicia Kort.

As the inventions and innovations springing out of Silicon Valley become more ingrained in our lives, San Francisco has become the most expensive city in which to start a business in America, surpassing both New York City and Los Angeles in office rental prices. According to Forbes, technology services and electronics are the second and fourth most profitable industries in the U.S., respectively, and tech start-up culture has become familiar enough to be lampooned in the media and on HBO. This was, obviously, not always the case.
In the 1930s, the Bay Area (along with the rest of America) was devoid of tech companies. The main attraction along the coast of what was then called “The Valley of Heart’s Delight” was the miles of fruit trees that lined the roads, providing work for many young immigrant families.

 

When the Depression hit, Heart’s Delight was devastated. The fruit industry struggled more than most until the overall economy saw an uptick during World War II. After years of downturn, Heart’s Delight suddenly became a great place to put weapons technology companies—in part thanks to the proximity of professors at universities like Stanford. A group of technology-based companies moved west and settled in the fertile Valley, ready to grow a new industry from the ground up.
Back east in postwar New York and New Jersey at Bell Labs—founded by Alexander Graham Bell—a trio was working on an invention that would be the first major step in creating machines that were both more accessible and more powerful than the ones used by the Allies during World War II. William Shockley, John Bardeen and Walter Brattain were searching for an alternative to vacuum tubes, which were constantly overheating while supplying energy to the machines. While Shockley was out of the office, Bardeen and Brattain solved the problem when they realized silicon was the perfect medium for conducting electrons, and discovered they could turn the flow of electricity on and off by using a circuit. They called their creation the transistor. Bell Labs filed a patent immediately, but Shockley was not included on it.
A temperamental, headstrong researcher, Shockley was furious. He shunned his two teammates and decided to work alone on a transistor that could be sold commercially. He unveiled his creation, dubbed the junction transistor—which had a “sandwich” structure with positive electrons sandwiching the negative electron between them—in 1951. Finally receiving the attention he desired, Shockley left Bell Labs in 1956 to move to Mountain View, California, to start his own endeavor: Shockley Semiconductor Laboratory.
The location was chosen mainly out of convenience (Shockley’s mother was ill and lived in the area), but it would have a major impact on the region and the industry. “It was the 13th of February 1956 when Beckman and Shockley signed the formal agreement to do this, and the announcement was made the next day, February 14,” said David Laws, curator at the Computer History Museum, about the date Silicon Valley was founded. “That was really the defining moment, when it was decreed the silicon device would be made in Silicon Valley.”
After it was official, Shockley hired eight Ph.D. researchers, including Robert Noyce, Jean Hoerni and Gordon Moore, to investigate if silicon could be used as a material in semiconductors. Not long into their new jobs at Shockley Semiconductor, the eight researchers noticed that, after Shockley won his Nobel Prize, their boss had become erratic and paranoid. They couldn’t stand working with him, so much so that they went to Arnold Beckman and declared they would only stay if Shockley was pushed out of the company. Beckman sided with his partner, and the “Traitorous Eight” made good on their word and sought out a new opportunity. Sherman Fairchild, owner of Fairchild Aircraft and Fairchild Camera, was the one who presented it. He told the group they should start their own company, and he would front the money. Thus, Fairchild Semiconductors was born. It was a landmark hire.
In 1957, despite the fact that transistors had replaced vacuum tubes, solving a problem which had been plaguing engineers for years, there was a larger obstacle ahead. Transistors had to be carefully hand wired and soldered together, and if any wire was out of place, the transistor would not work. Each wire represented a “yes” or “no” switch: In order to solve a complex problem or program a task, there needed to be more “yeses” and “nos,” so more and more wires were used. Transistors were also made of three parts that always needed to be wired together: the emitter, base and collector. In order to solve more complex problems, contrary to the slimming and shrinking of devices we see so often today, computers were getting larger. But even the biggest machines were only so big. The idea of the personal computer had already been conceived, but it agonizingly could not be executed due to this “tyranny of numbers.”
The entire world was racing to solve the problem, and two teams of engineers reached the finish within months of each other: Fairchild Semiconductor, led by Robert Noyce, and Texas Instruments, led by Jack Kilby.
Shortly after starting his job at TI, Kilby was relatively alone in the office, the rest of the staff taking advantage of summer vacation. It seemed silly to Kilby to separate the emitter, base and collector parts of the transistor and then attempt to wire them together. He realized they would be more powerful and stable on one piece of silicon, but he still had to figure out how to incorporate the transistor into the chip.
Meanwhile, Fairchild’s Jean Hoerni had this exact same breakthrough. “Jean Hoerni invented a way of making integrated circuits, called the planar process, which absolutely revolutionized the building of semiconductors,” says Laws. “It turned it from a handcrafted, one-at-a-time operation into a mass highballing production and continues to be the essence of the way chips are made today, 60 years later.”

The planar process used a thin layer of oxidized silicon on top of the circuit to cement the chip into place. The wires could then be put in place like candles on top of a cake, instead of painstakingly soldered one by one.
Months later, Noyce and Kilby made the discoveries that would complete the integrated circuit, but Texas Instruments was much quicker to submit the idea to the Patent Office. Of course, Fairchild fought to get credit. Noyce was ultimately awarded the patent, on the grounds that he had better drawings and had produced it on a machine (rather than by hand like Kilby did). Still, the patent victory was more symbolic than monetary in nature. Both companies were seeing unheard of profits for their computer chips. Kilby continued to work at Texas Instruments for decades more, while Noyce went on to found Intel and create another landmark technology, the microprocessor.
But Kilby and Noyce’s original innovations, these little computer chips, have changed very little in the last 60 years. They power your smartphone, computer and even your kitchen appliances. Without the pioneers who created them, future founding fathers such as Bill Gates and Mark Zuckerberg would have had nothing upon which to build their empires.

http://www.newsweek.com/silicon-valley-microchip-modern-technology-437992

Multi-Beam Market Heats Up

The multi-beam e-beam mask writer business is heating up, as Intel and NuFlare have separately entered the emerging market.
In one surprising move, Intel is in the process of acquiring IMS Nanofabrication, a multi-beam e-beam equipment vendor. And separately, e-beam giant NuFlare recently disclosed its new multi-beam mask writer technology.
As a result of the moves, the Intel/IMS duo and NuFlare will now race each other to bring multi-beam mask writers into the market. Still in the R&D stage, these newfangled tools promise to speed up the write times for next-generation photomasks, although there are still challenges to bring this technology into production.
Intel, for one, sees a need for this technology. “Intel is completing its acquisition of IMS Nanofabrication,” according to officials from Intel. “This transaction will allow IMS Nanofabrication to focus on and accelerate the development of [multi-beam mask writing], which is a critical technology for securing the extension of Moore’s Law well into the future.”
To be sure, though, Intel’s move to acquire IMS took the industry by surprise. For one thing, Intel has invested in equipment suppliers in the past, but the company hasn’t bought a tool vendor outright in recent memory.
With IMS, Intel has taken a step into the equipment business. But it’s unlikely that the chip giant will make other acquisitions in the sector in the near term, according to analysts. The IMS deal is perhaps a one-time strategic move in a critical area, analysts said.
In any case, the move also represents Intel’s latest investment related to extreme ultraviolet (EUV) lithography. Indeed, Intel and others are placing huge bets on EUV. And to ensure the EUV infrastructure is ready, Intel and others have invested in various companies, such as ASML as well as Inpria, an EUV resist developer.
IMS’ technology is also expected to play a role for both EUV and optical masks. For years, Intel and other leading-edge chipmakers have produced photomasks within their own, internal mask shops.
Mask makers use traditional single-beam e-beam tools to pattern a photomask. But recently, e-beams have been struggling to keep up with complex masks.
In response, Intel and Photronics invested in IMS in 2011. In addition, Intel, DNP, Photronics and TSMC are collaborating on an effort to accelerate IMS’ multi-beam mask writer tools in the market. Still in the R&D stage, IMS’ technology makes use of multiple beams, which in theory will accelerate the write times in mask production.
Reports surfaced, however, that IMS recently fell behind schedule with its tool program amid technical issues, according to multiple sources. So to help IMS get back on track, Intel moved to secure the technology by acquiring IMS, sources said.
Meanwhile, under the terms of the deal, IMS will operate as a subsidiary of Intel. IMS will continue its “collaborative efforts and supporting their other industry customers,” according to Intel, which declined to comment further on the deal. IMS also declined to comment.
As part of Intel, though, IMS may encounter some difficulties in terms of selling its tools to Intel’s competitors that have mask shops, such as GlobalFoundries, Samsung, SK Hynix, SMIC, Toshiba and TSMC. That could open the door for NuFlare and its multi-beam tool. On the other hand, photomask makers welcome the idea of having two strong multi-beam vendors in the market.
All told, mask makers have high hopes for multi-beam mask writers. “Because everybody thinks multi-beam mask writing will happen, people are investing more as a result of the technology,” said Aki Fujimura, chief executive of D2S, in a recent interview. “The OPC community can do more creative things without the constraint of the mask being able to write in a reasonable time.”
The first multi-beam mask writers could move into early production by late 2016. These tools are expected to move into high-volume production by 2018, according to a survey from the eBeam Initiative.
Still, the questions are clear. Will multi-beam mask writer technology work as advertised? And what does it bring to the party?
Why multi-beam?
E-beams are used in the production of photomasks. Basically, a photomask consists of a chrome layer on a glass substrate.
In the flow, the photomask is patterned based on the specs of a given IC design. The mask, in turn, becomes a master template for that design. After a mask is patterned, it is shipped to the fab. The mask is placed in a lithography tool. The tool projects light through the mask, which, in turn, patterns the images on a wafer.
There are two types of systems that pattern the features on a mask—e-beams and laser-based pattern generators. E-beams are used to pattern critical layers, while laser-based tools are geared for non-critical layers.
Single-beam e-beam tools are based on variable shape beam (VSB) technology. In VSB, two shaped apertures are used to form a triangular or rectangular beam.
Not long ago, the e-beam could pattern a mask with ease. But recently, it’s become a different story. “Mask making is becoming increasingly difficult,” Fujimura said. “The big point is that complexity is growing for mask makers.”
As before, the lithography type determines the mask specs. Today, chipmakers are extending 193nm wavelength lithography to 16nm/14nm and beyond.
To deal with the diffraction issues, mask makers must use various reticle enhancement techniques (RETs). One RET, called optical proximity correction (OPC), is used to modify the mask patterns to improve the printability on the wafer. OPC makes use of tiny assist features on the mask. And the features are getting smaller and more complex at each node.
Mask makers are also moving towards inverse lithography technology (ILT). ILT boosts the pattern fidelity on the mask. But it also involves the creation of more complex curvilinear features on the mask.
As the mask becomes more complex, photomask makers are seeing an increase in write times. Writes times—the key metric in mask production—determine how fast an e-beam can write a mask layer. Write times are dependent on the number of e-beam shots required to pattern a mask layout. If a mask is complex, it requires more shots.
From 2001 to 2005, e-beam write times were 8 hours per mask set. In 2015, the average mask write times were 9.6 hours, according to the eBeam Initiative survey. The write times for more complex masks range from 18 to 72 hours today, according to the survey.
Since 2011, the write times have increased by 25%, due to mask complexity. This, in turn, impacts mask turnaround times and cost.
Mask makers have found ways to solve these issues. For example, chipmakers moved to multiple patterning starting at 20nm. In multi-patterning, the mask is split into two or more mask layers.
To solve the problem, some mask shops simply buy more e-beams. In some cases, they are simultaneously utilizing two e-beams on the same mask. The e-beams write different layers in parallel to reduce the cycle times and cost.
There are other ways to reduce write times. Over the years, e-beam vendors have made their systems faster by increasing the current densities in a tool. NuFlare, for example, has significantly boosted the current densities in its single-beam tool over the last decade, from 70A/cm² in 2006 to 1,200A/cm² today.
“It’s amazing what the e-beam can do today,” said Franklin Kalk, executive vice president of technology at Toppan Photomasks. “Shaped beam tools are accurate. They have placement accuracies in the low single digits now. The CD accuracies are almost immeasurable.”
But in some respects, today’s single-beam e-beams have hit a physical limit. “The end of current density scaling for shaped beam is about 1200A/cm²,” Kalk said. “Beyond that, you have to go to multi-beam.”
It’s possible to develop a tool beyond 1200A/cm². But as the current densities increase beyond a certain figure, the shot size becomes too small. “At some point, that doesn’t really help you anymore,” Kalk said.
In fact, NuFlare’s latest tool, called the EBM-9500, has a current density of 1,200A/cm². This tool, according to NuFlare, represents the company’s last single-beam system.
All told, single-beam e-beam is expected to run out of steam at 7nm or 5nm, according to analysts. Then, mask makers will require multi-beam mask writers, especially for EUV photomasks.
For example, with today’s single-beam tools, EUV mask write times could range from 50 to 100 hours just for one leading-edge mask, a figure that is unacceptable in the industry, analysts said. In contrast, multi-beam mask writers promise to keep the write times down to a few hours or a half-day for all mask types.
Lab to the mask shop?
Bringing multi-beam mask writers from the lab to the mask shop is challenging. Indeed, after nearly a decade in R&D, these systems are still not in production amid a number of technical challenges.
Today, two entities, Intel/IMS and NuFlare, are separately developing multi-beam mask writers. For some time, IMS has been developing a system with 262,144 programmable beams. The 50-keV tool has demonstrated a half-pitch resolution of 30nm.
In 2013, IMS joined forces with JEOL to co-develop tools. IMS provides its multi-beam technology, while JEOL is the systems integrator. The goal is to ship a high-volume mask writer in 2016.
Meanwhile, NuFlare recently disclosed the details of its multi-beam tool. The 50-KeV system, dubbed the MBM-1000, consists of roughly 250,000 beams, according to Hiroshi Matsumoto of NuFlare. The tool, which is geared for 5nm, will ship in late 2017.
Intel/IMS and NuFlare both promise half-day write times, but they are taking different approaches. NuFlare’s tool performs the blanking functions at low voltage and then accelerates the current. In contrast, the Intel/IMS tool accelerates the current and then does the blanking.
Both vendors face similar challenges. “The nice thing about a multi-beam tool is that it is a deterministic machine,” Toppan’s Kalk said. “As long as you get the data down the datapath, it will write a mask in a time that’s determined by the overall area of the pattern you are writing.”
The big challenge is to move that data down the datapath. “It is not trivial to put down a quarter million beams with perfect fidelity and timing at high speeds. You are also talking about writing a mask in say 12, 14 or 15 hours,” he said. “That’s a lot of data to put down in the pipeline. The datapath is going to be critical. If we can’t get the data to the beam lines, it will slow (the system) down.”
There are other challenges. If or when the industry inserts EUV for production, mask makers must contend with the complexities of EUV masks. For EUV, the sub‐resolution assist feature (SRAF) sizes on the mask range from 32nm to 40nm, compared to 60nm for optical. The SRAF 1x design sizes range from 8nm to 10nm for EUV, compared to 15nm for optical, according to Mentor Graphics.
“Minimum feature size on the mask will decrease since k1 decreases, affecting both primary features and assist features,” said Peter Buck, manager of MDP and platform solutions at Mentor Graphics. “Mask layout specific compensation for EUV-specific optical effects, such as shadowing, flare and black border, may require full-mask layout OPC and will require full-mask layout MPC and fracture.”
Needless to say, EUV masks are complex. On the other hand, EUV masks will require fewer masks per set. So, in theory, a multi-beam mask writer could keep EUV mask write times in check.
But mask makers may want to keep their single-beam tools around for EUV, especially if the multi-beam tools are late or fall short of their promises. “While multi-beam writers are targeted to be faster than VSB writers for advanced layers, the complexity of massively-parallel e-beam writers makes these tools challenging to produce,” Buck said. “Innovation for VSB writers continues. It seems likely that both technologies will have significant roles to play in both advanced DUV and EUV mask lithography.”
Multi-beam mask writers are just one part of what’s required to make EUV happen in the mask shop. In the EUV mask infrastructure, the industry has made progress in some but not all areas.
EUV mask blanks are a bright spot. Last year, there were an average of 10 defects on an EUV mask blank, said Seong-Sue Kim, a technical staff member within the Semiconductor R&D Center at Samsung.
The industry hopes to bring that figure down to five defects, which can be achieved within the next year, Kim said. “There has been continued progress in blank defectivity,” he said.
Still, there are some major gaps. “Mask defects are still a key issue,” said Rich Wise, technical managing director at Lam Research. “You need actinic inspection.”
The industry is begging for actinic-based pattern mask inspection for EUV, but no such tool exists. So for now, the industry must use today’s optical and e-beam inspection to inspect EUV masks. “The best idea is to extend the existing platforms,” said Yalin Xiong, general manager of the Reticle Products Division at KLA-Tencor. “For the short term, this solution is good enough.”
Nevertheless, there are other technologies that must come together before EUV moves into production. EUV is targeted at 7nm or 5nm. “The source power is making progress, but there is still work to do,” Lam’s Wise said.
Yet most say it’s a matter of if and not when EUV will move into production. “EUV is making huge progress,” said David Fried, chief technology officer at Coventor, a supplier of predictive modeling tools. “For example, you have the pellicle, resist defectivity and other issues. Those things were dark clouds a few years ago. Now, the problems are clearly defined and there are competing solutions. People are working on them and those will be solved.”

http://semiengineering.com/multi-beam-market-heats-up/

Ready For Nanoimprint?

Nanoimprint has been discussed, debated, and hyped since the term was first introduced in 1996. Now, a full 20 years later, it is being taken much more seriously in light of increasing photomask costs and delays in bringing alternatives to market.
Nanoimprint lithography is something like a hot embossing process. The structures are patterned onto a template or mold using an e-beam or scanner, and then pressed into a resist on a substrate. After that, the template is removed. In semiconductor lithography, this is a relatively simple process by comparison, which is why it has attracted so much attention.
Resolution has been well documented for this technology. But other key metrics—throughput, overlay and defect density—are still unproven. And that has set off a flurry of activity around nanoimprint, notably from Canon and Toshiba.
Canon’s imprint process is very different from conventional lithography. It starts with a pattern that is formed by ink-jetting drops of a UV-curable resist. A mold with the desired pattern is lowered into the liquid, which fills the mold. The resist is cured by a flash of UV light, and the mold is then separated from the pattern.
The process was invented at the University of Texas and was refined by the venture-funded startup Molecular Imprints. Canon acquired Molecular imprints in 2014. The challenges for imprint were obvious from the start. Could the liquid spread quickly? Could the patterns be overlaid to within single nanometers? Could the mechanical molding process be clean enough to yield devices? And could the 1x molds be made defect-free?
So where are we with throughput?
“We have developed a cluster tool system with four imprint heads and four stages,” said Kazunori Iwamoto, deputy group executive at Canon, in an interview last month at the Advanced Lithography Symposium. “The throughput has improved from [40 x300 mm is that 300mm wafers] wafers per hour in 2014 to 60 wafers per hour in 2016. What’s more, this platform will achieve more than 80 wafers per hour in 2017.
Iwamoto explained the throughput improvement comes from faster filling times of the imprint resist into the mold. To reduce the filling time, a faster spread of the imprint liquid is required.
Two techniques were described in this conference. One is the combination of a smaller drop volume (1 picoliter) and high drop density. This reduces the air bubbles during filling. The other was the development of a new imprint resist with faster spread and filling times. The throughput, imprint uniformity and defect density are also improved by design for imprint, or DFI.
“We do have some simple layout design rules,” explained Mark Melliar-Smith, CEO of Canon Nanotechnology (formerly Molecular Imprints). “The spread of the imprint liquid is sensitive to pattern density, so we require the use of dummy features in large, unpatterned areas much like CMP. We also require the top surface to be flat to similar tolerance for DOF (depth of focus) for 193 litho.”
Melliar-Smith emphasized that there were no additional constraints on scribe lines. “Our customers would not tolerate any changes.”
A separate element to design for imprint is drop-pattern management. “We have developed software to design the drop pattern to match the fill of the pattern, eliminate the trapping of air bubbles, and speeding up the spreading step,” Melliar-Smith said.
That will be critical for improving wafer throughput. Iwamoto said that the long-term goal of 200 wafers per hour will require larger imprint fields.
Overlay
One piece that is critical to this whole process is overlay, which is the ability of a lithography scanner to align and print the various layers accurately on top of each other.
“Current mix and match overlay (MMO) is at 4.8nm 3 sigma, and the goal for next year is 4nm which will meet production targets for NAND and DRAM,” said Iwamoto. “In 2018 MMO will improve further to less than 3.5nm.”
He noted that the current MMO error includes a large wafer distortion error coming from the prior lithographic levels. Reduction of that error is key to MMO improvement. Canon has developed something called High Order Correction (HOC), and also a new wafer chuck for imprint. The HOC correction system uses a second light source that can be modulated using a digital mirror device. The light locally heats the wafer and mask, and because of the difference in expansion thermal coefficient, local wafer distortion corrections can be made.
He showed data that HOC reduced wafer distortion errors in a single field from 2.5 nm to 0.67nm. “In addition, we developed a new wafer chuck to improve the flatness around the wafer edge by using special tooling, to help us to meet production overlay specification.”
Defects
There are three defects that Canon is concerned with—mask, in process random, and in process adders often expressed as mask life.”
The company has demonstrated five defects cm² for a 2xnm half pitch pattern, using masks made by DNP. The goal for engineering release is 1 percm², and production release 0.1 per cm².
In a presentation Toshiba showed lower values of 1 defect cm². MS suggested that the lower value measured by Toshiba was probably a reflection of the production environment at Toshiba. The causes of these defects were ion contamination and trapped surface bubbles, and they are working on mitigation. Toshiba also showed a 4 wafer run with no added repeating defects, a critical capability.
In a presentation, DNP presented data on 2x nm masks and mask copies.
They have made 2x nm patterns with a 1-2 defects per mask by using the current mask replication tool. An audience member asked “are you ready for production?”
Answer “yes”.
DNP also showed data for 1x nm parts with 10 defects per mask. There was a discussion of this problem caused by trying to separate 2 stiff mask blanks.
“I have complete confidence that the 1xnm will be as good as 2x nm very quickly. We understand the problem and DNP is making rapid progress,” said Melliar-Smith.
Iwamoto emphasized that Canon is just now developing a new mask replication tool to support a mass production towards 1xnm.
Finally, Iwamoto showed results for airborne particle adders as an indicator for mask life. Canon has applied its materials expertise to treat equipment surfaces and has developed an air curtain around the imprint head to protect the wafer. “The results suggest a mask life in excess of 1,000 wafers, the production goal,” said Melliar-Smith
There are two early adopters of the technology, Toshiba and Hynix. Canon says that is enough to reach critical mass for high-volume manufacturing. “We have to start small and grow,” Melliar-Smith said. “Today, we probably do not have the bandwidth for many more customers. If we can continue to show progress, other customers will be interested, and if we can get defects down another 100X, we can even use this for logic.”
EUV also is making progress, but probably only has 1 generation before it has to add multi-patterning or much larger NA. “We think imprint has a long term future with resolution below 10nm, no shot noise, minimal layout constraints, and the potential of increasing throughput from larger fields that are not possible with optics,” he said.
Long time in development
Tatsuhiko Higashiki, of Toshiba’s Research and Development Center, began the imprint program inside of Toshiba a decade ago.
“Ten years ago, I was approached by my colleagues, to help them find a way to pattern 30nm pitch and below, which was beyond immersion at that time, and multi patterning and EUVL had not been developed,” said Higashiki. “I was researching high-resolution lithography such like interferometric lithography for the whole 300mm wafer area. However, the technology can expose only dense patterns. Suddenly Molecular Imprints visited me and I saw a way to create small test structures using a relatively inexpensive tool, so we started with an Imprio 200 system. At the time I did not imagine that imprint could be used as a high volume manufacturing tool.”
By February 2011, there were papers at the SPIE Advanced Lithography conference by Toshiba reporting on their results using a MII system. MII reported on shipping an imprint module that was being integrated by their equipment partner. Canon reported on their evaluation of their MII system. http://semiengineering.com/imprint-ngl/
In February 2014, it was announced that Canon was acquiring the semiconductor operations of Molecular Imprints. And in February 2015, Toshiba signed a definitive agreement with SK Hynix on joint development of next-generation lithography, targeting practical use in 2017.
“Last year, Toshiba presented in SPIE2015 that we tried a working memory device, with the critical layer patterned using a Canon imprint ADT (advanced development technology) tool. “I have confidence to imprint as a future patterning solution,” said Higashiki. “Today we have 50 companies in the supply chain engaged in imprint. We have added several imprint ADT tools on a Canon platform with an MII Imprint head. “
Toshiba talked about the growth in the ecosystem, which today includes Shibaura (mask etcher), NuFlare (EB writer and mask inspection), as well as Canon, TEL, Zeon, TOK, Fuji Film and JSR.
But there is more work ahead, Higashiki noted. “To run production in memory, today’s defect density of 5 cm² must come down by 5X. This is still 100X higher than the level needed for logic. The higher defect tolerance is a direct result of error correction software that runs on memory. Overlay will be at 2 to 3 nm which will be good enough for memory.”
The template also requires much work as it remains very demanding for resolution, distortion and defects. This requires access to a very specialized set of process equipment to be successful.

http://semiengineering.com/ready-for-nanoimprint/

After PCs and mobile, a chip battle for VR devices is brewing

Millions of people will buy VR headsets in the coming years to play games and view 3D content, and those sales could spark a real-world war among chip-makers.
Some new VR headsets announced at this week's Game Developers Conference in San Francisco are full-on computers, and others need to be hooked up to PCs with powerful graphics cards, similar to Oculus Rift.
The VR devices, designed for gaming and for roaming 3D worlds, are a showcase for the graphics technologies of chip makers like AMD and Qualcomm.
The headsets set up a battle in the fast-growing VR space among chip makers, which also include Intel and Nvidia. The war among chip makers comes with a twist because it places a large on emphasis on GPUs, which are important for rendering 4K video and 3D content.
The Sulon Q headset, announced this week, is a full computer in a headset for VR and augmented reality, and it runs on AMD's chips code-named Carrizo. The headset is similar to Microsoft's HoloLens, and it allows users to interact with 3D objects that show up as floating images, much like holographic projections. It has a 2560 x 1440 OLED display and a graphics processor that can run high-end games.
But with PC components crammed into the headset, questions remain about whether it will heat up and be uncomfortable to wear.
The Carrizo chips include a lighter version of the high-powered Radeon GPUs used in desktops linked to Oculus Rift VR headsets. AMD believes VR headsets will need powerful on-board graphics processors for life-like images and high frame rates, or else the experience could get nauseating.
By comparison, Microsoft's HoloLens, which will ship soon, has a low-power Intel processor code-named Cherry Trail, designed for tablets. The GPU in Cherry Trail isn't as powerful as the AMD GPU in Sulon Q, but provides the HoloLens with a longer battery life. The HoloLens is focused more on blending real and virtual worlds than on high-end gaming.

Qualcomm's latest Snapdragon 820 chip -- which is in smartphones like Samsung's latest Galaxy S7 -- is also coming to VR headsets.
A headset from China-based Goertek is among the first with a Snapdragron 820 chip, which is capable of rendering 4K video and 360-degree interactive video.
"Several other VR devices that use Snapdragon 820 will be announced later this year," Tim Leland, vice president for product management at Qualcomm, said in an email.
Right now, most of the VR headset chips are adapted from those found in mobile devices or PCs. But if VR headset shipments hit tens of millions of units, Intel, AMD and Qualcomm may develop specialized chips, said Nathan Brookwood, principal analyst at Insight 64.
Making chips can be expensive, and the economics have to make sense, Brookwood said.
But the rise of VR reinforces the importance of visual computing and graphics processors, Brookwood said.
Gartner is projecting VR headset shipments to reach 1.4 million this year, growing from 140,000 in 2015. Shipments will grow to 6.3 million by 2017, the company predicts.

http://www.pcworld.com/article/3044522/hardware/after-pcs-and-mobile-a-chip-battle-for-vr-devices-is-brewing.html