Ready For Nanoimprint?

Nanoimprint has been discussed, debated, and hyped since the term was first introduced in 1996. Now, a full 20 years later, it is being taken much more seriously in light of increasing photomask costs and delays in bringing alternatives to market.
Nanoimprint lithography is something like a hot embossing process. The structures are patterned onto a template or mold using an e-beam or scanner, and then pressed into a resist on a substrate. After that, the template is removed. In semiconductor lithography, this is a relatively simple process by comparison, which is why it has attracted so much attention.
Resolution has been well documented for this technology. But other key metrics—throughput, overlay and defect density—are still unproven. And that has set off a flurry of activity around nanoimprint, notably from Canon and Toshiba.
Canon’s imprint process is very different from conventional lithography. It starts with a pattern that is formed by ink-jetting drops of a UV-curable resist. A mold with the desired pattern is lowered into the liquid, which fills the mold. The resist is cured by a flash of UV light, and the mold is then separated from the pattern.
The process was invented at the University of Texas and was refined by the venture-funded startup Molecular Imprints. Canon acquired Molecular imprints in 2014. The challenges for imprint were obvious from the start. Could the liquid spread quickly? Could the patterns be overlaid to within single nanometers? Could the mechanical molding process be clean enough to yield devices? And could the 1x molds be made defect-free?
So where are we with throughput?
“We have developed a cluster tool system with four imprint heads and four stages,” said Kazunori Iwamoto, deputy group executive at Canon, in an interview last month at the Advanced Lithography Symposium. “The throughput has improved from [40 x300 mm is that 300mm wafers] wafers per hour in 2014 to 60 wafers per hour in 2016. What’s more, this platform will achieve more than 80 wafers per hour in 2017.
Iwamoto explained the throughput improvement comes from faster filling times of the imprint resist into the mold. To reduce the filling time, a faster spread of the imprint liquid is required.
Two techniques were described in this conference. One is the combination of a smaller drop volume (1 picoliter) and high drop density. This reduces the air bubbles during filling. The other was the development of a new imprint resist with faster spread and filling times. The throughput, imprint uniformity and defect density are also improved by design for imprint, or DFI.
“We do have some simple layout design rules,” explained Mark Melliar-Smith, CEO of Canon Nanotechnology (formerly Molecular Imprints). “The spread of the imprint liquid is sensitive to pattern density, so we require the use of dummy features in large, unpatterned areas much like CMP. We also require the top surface to be flat to similar tolerance for DOF (depth of focus) for 193 litho.”
Melliar-Smith emphasized that there were no additional constraints on scribe lines. “Our customers would not tolerate any changes.”
A separate element to design for imprint is drop-pattern management. “We have developed software to design the drop pattern to match the fill of the pattern, eliminate the trapping of air bubbles, and speeding up the spreading step,” Melliar-Smith said.
That will be critical for improving wafer throughput. Iwamoto said that the long-term goal of 200 wafers per hour will require larger imprint fields.
Overlay
One piece that is critical to this whole process is overlay, which is the ability of a lithography scanner to align and print the various layers accurately on top of each other.
“Current mix and match overlay (MMO) is at 4.8nm 3 sigma, and the goal for next year is 4nm which will meet production targets for NAND and DRAM,” said Iwamoto. “In 2018 MMO will improve further to less than 3.5nm.”
He noted that the current MMO error includes a large wafer distortion error coming from the prior lithographic levels. Reduction of that error is key to MMO improvement. Canon has developed something called High Order Correction (HOC), and also a new wafer chuck for imprint. The HOC correction system uses a second light source that can be modulated using a digital mirror device. The light locally heats the wafer and mask, and because of the difference in expansion thermal coefficient, local wafer distortion corrections can be made.
He showed data that HOC reduced wafer distortion errors in a single field from 2.5 nm to 0.67nm. “In addition, we developed a new wafer chuck to improve the flatness around the wafer edge by using special tooling, to help us to meet production overlay specification.”
Defects
There are three defects that Canon is concerned with—mask, in process random, and in process adders often expressed as mask life.”
The company has demonstrated five defects cm² for a 2xnm half pitch pattern, using masks made by DNP. The goal for engineering release is 1 percm², and production release 0.1 per cm².
In a presentation Toshiba showed lower values of 1 defect cm². MS suggested that the lower value measured by Toshiba was probably a reflection of the production environment at Toshiba. The causes of these defects were ion contamination and trapped surface bubbles, and they are working on mitigation. Toshiba also showed a 4 wafer run with no added repeating defects, a critical capability.
In a presentation, DNP presented data on 2x nm masks and mask copies.
They have made 2x nm patterns with a 1-2 defects per mask by using the current mask replication tool. An audience member asked “are you ready for production?”
Answer “yes”.
DNP also showed data for 1x nm parts with 10 defects per mask. There was a discussion of this problem caused by trying to separate 2 stiff mask blanks.
“I have complete confidence that the 1xnm will be as good as 2x nm very quickly. We understand the problem and DNP is making rapid progress,” said Melliar-Smith.
Iwamoto emphasized that Canon is just now developing a new mask replication tool to support a mass production towards 1xnm.
Finally, Iwamoto showed results for airborne particle adders as an indicator for mask life. Canon has applied its materials expertise to treat equipment surfaces and has developed an air curtain around the imprint head to protect the wafer. “The results suggest a mask life in excess of 1,000 wafers, the production goal,” said Melliar-Smith
There are two early adopters of the technology, Toshiba and Hynix. Canon says that is enough to reach critical mass for high-volume manufacturing. “We have to start small and grow,” Melliar-Smith said. “Today, we probably do not have the bandwidth for many more customers. If we can continue to show progress, other customers will be interested, and if we can get defects down another 100X, we can even use this for logic.”
EUV also is making progress, but probably only has 1 generation before it has to add multi-patterning or much larger NA. “We think imprint has a long term future with resolution below 10nm, no shot noise, minimal layout constraints, and the potential of increasing throughput from larger fields that are not possible with optics,” he said.
Long time in development
Tatsuhiko Higashiki, of Toshiba’s Research and Development Center, began the imprint program inside of Toshiba a decade ago.
“Ten years ago, I was approached by my colleagues, to help them find a way to pattern 30nm pitch and below, which was beyond immersion at that time, and multi patterning and EUVL had not been developed,” said Higashiki. “I was researching high-resolution lithography such like interferometric lithography for the whole 300mm wafer area. However, the technology can expose only dense patterns. Suddenly Molecular Imprints visited me and I saw a way to create small test structures using a relatively inexpensive tool, so we started with an Imprio 200 system. At the time I did not imagine that imprint could be used as a high volume manufacturing tool.”
By February 2011, there were papers at the SPIE Advanced Lithography conference by Toshiba reporting on their results using a MII system. MII reported on shipping an imprint module that was being integrated by their equipment partner. Canon reported on their evaluation of their MII system. http://semiengineering.com/imprint-ngl/
In February 2014, it was announced that Canon was acquiring the semiconductor operations of Molecular Imprints. And in February 2015, Toshiba signed a definitive agreement with SK Hynix on joint development of next-generation lithography, targeting practical use in 2017.
“Last year, Toshiba presented in SPIE2015 that we tried a working memory device, with the critical layer patterned using a Canon imprint ADT (advanced development technology) tool. “I have confidence to imprint as a future patterning solution,” said Higashiki. “Today we have 50 companies in the supply chain engaged in imprint. We have added several imprint ADT tools on a Canon platform with an MII Imprint head. “
Toshiba talked about the growth in the ecosystem, which today includes Shibaura (mask etcher), NuFlare (EB writer and mask inspection), as well as Canon, TEL, Zeon, TOK, Fuji Film and JSR.
But there is more work ahead, Higashiki noted. “To run production in memory, today’s defect density of 5 cm² must come down by 5X. This is still 100X higher than the level needed for logic. The higher defect tolerance is a direct result of error correction software that runs on memory. Overlay will be at 2 to 3 nm which will be good enough for memory.”
The template also requires much work as it remains very demanding for resolution, distortion and defects. This requires access to a very specialized set of process equipment to be successful.

http://semiengineering.com/ready-for-nanoimprint/