Intel Bets It Can Turn Everyday Silicon into Quantum Computing’s Wonder Material

The world’s largest chip company sees a novel path toward computers of immense power.

Sometimes the solution to a problem is staring you in the face all along. Chip maker Intel is betting that will be true in the race to build quantum computers—machines that should offer immense processing power by exploiting the oddities of quantum mechanics.
Competitors IBM, Microsoft, and Google are all developing quantum components that are different from the ones crunching data in today’s computers. But Intel is trying to adapt the workhorse of existing computers, the silicon transistor, for the task.
Intel has a team of quantum hardware engineers in Portland, Oregon, who collaborate with researchers in the Netherlands, at TU Delft’s QuTech quantum research institute, under a $50 million grant established last year. Earlier this month Intel’s group reported that they can now layer the ultra-pure silicon needed for a quantum computer onto the standard wafers used in chip factories.
This strategy makes Intel an outlier among industry and academic groups working on qubits, as the basic components needed for quantum computers are known. Other companies can run code on prototype chips with several qubits made from superconducting circuits (see “Google’s Quantum Dream Machine”). No one has yet advanced silicon qubits that far.
A quantum computer would need to have thousands or millions of qubits to be broadly useful, though. And Jim Clarke, who leads Intel’s project as director of quantum hardware, argues that silicon qubits are more likely to get to that point (although Intel is also doing some research on superconducting qubits). One thing in silicon’s favor, he says: the expertise and equipment used to make conventional chips with billions of identical transistors should allow work on perfecting and scaling up silicon qubits to progress quickly.
Intel’s silicon qubits represent data in a quantum property called the “spin” of a single electron trapped inside a modified version of the transistors in its existing commercial chips. “The hope is that if we make the best transistors, then with a few material and design changes we can make the best qubits,” says Clarke.
Another reason to work on silicon qubits is that they should be more reliable than the superconducting equivalents. Still, all qubits are error prone because they work on data using very weak quantum effects (see “Google Researchers Make Quantum Components More Reliable”).
The new process that helps Intel experiment with silicon qubits on standard chip wafers, developed with the materials companies Urenco and Air Liquide, should help speed up its research, says Andrew Dzurak, who works on silicon qubits at the University of New South Wales in Australia. “To get to hundreds of thousands of qubits, we will need incredible engineering reliability, and that is the hallmark of the semiconductor industry,” he says.
Companies developing superconducting qubits also make them using existing chip fabrication methods. But the resulting devices are larger than transistors, and there is no template for how to manufacture and package them up in large numbers, says Dzurak.
Chad Rigetti, founder and CEO of Rigetti Computing, a startup working on superconducting qubits similar to those Google and IBM are developing, agrees that this presents a challenge. But he argues that his chosen technology’s head start will afford ample time and resources to tackle the problem.
Google and Rigetti have both said that in just a few years they could build a quantum chip with tens or hundreds of qubits that dramatically outperforms conventional computers on certain problems, even doing useful work on problems in chemistry or machine learning.

https://www.technologyreview.com/s/603165/intel-bets-it-can-turn-everyday-silicon-into-quantum-computings-wonder-material/?utm_campaign=internal&utm_medium=homepage&utm_source=top-stories_1

Memory Drives Chip Growth

SAN JOSE, Calif. – Sales of memory chips will increase 10% next year to a new record high of $85.3 billion, according to the latest report from IC Insights. Increases are forecast to continue with sales reaching nearly $110.0 billion in 2021.

Thanks to both rising prices and volume sales, the memory sector is expected to lead overall semiconductor sales growth. The average annual growth rate for the memory market is forecast to be 7.3% from 2016-2021, about 2.4 points higher than the total IC market during the period, the market watcher predicts.
IC Insights forecasts memory unit sales to grow at a 5.6% compound rate. Average selling prices will increase in all but one year (2020) through the forecast at an average annual rate of 1.8%, it said.

A decline in PC sales, the biggest user of memory chips, caused excess inventory and price declines in late 2015, leading to a 3% decline to $78.0 billion for memory chips that year. The fall came despite supplier consolidation, the lack of new capacity and rising emerging markets which normally boost the memory sector.
Weak market conditions began to improve in the middle of this year, though the memory sector is still expected to decline 1% in 2016. Average selling prices fell 3% last year and another 10% this year. NAND flash is the only memory segment expected to show growth in 2016.
— Rick Merritt, Silicon Valley Bureau Chief, EE Times
http://www.eetimes.com/document.asp?doc_id=1331034

The Inotera model unlikely to be implemented in China, says Micron CEO

For Micron Technology, it is no longer meaningful to implement the "Inotera Memories model" in China, according to Mark Durcan, CEO for the US memory vendor.

The so-called Inotera model sees Micron receive licensing fees and a portion of memory production capacity from partners which lack sufficient technology but are capable of scaling up output with huge capital.

Micron already has enough DRAM production capacity and economies of scale, and having another partner like the pre-acquisition Inotera is no longer meaningful for the company, said Durcan. Micron's principle is to protect the interests of shareholders and the team, while avoiding destabilizing the industry supply-demand balance, Durcan continued.

In fact, the joint venture deal betwen Micron and Nanya Technology was quite successful. Inotera was allowed to expand its DRAM production capacity with technology licensed from Micron and capital from Nanya, and Micron and Nanya were both able to expand their respective output and global market share.

Nevertheless, the current circumstances are different as DRAM prices have become more stable, and Micron's production base worldwide has expanded substantially, Durcan said.

Micron recently completed acquiring Inotera, formerly a Taiwan-based production partner of the US firm. Previously, Micron took over Taiwan-based Rexchip Electronics as a result of its acquisition of Japan's Elpida Memory. Taiwan now accounts for more than 60% of Micron's overall DRAM production capacity, which is mostly Micron's leading-edge capacity, Durcan said.

At the same time, China is aggressively developing its homegrown chipmaking industry including the memory sector. State-backed Tsinghua Unigroup had previously proposed a more than US$20 billion bid for Micron, but the offer is believed to have been turned down. Nevertheless, China remains aggressive in building its homegrown technology for making DRAM chips.

China will definitely be capable of finding a partner like Micron to license technology and make joint investments with, but for Micron, it would be appropriate to implement such a model 10 years ago when the DRAM industry was still immature and very competitive, Durcan noted. The industry has now entered its mature stage, and the chip prices tend to grow at a relatively stable rate. For Micron, there is less reason to be in that kind of relationship than there was 10 years ago, Durcan added.

However, such a joint-venture model may make more sense in the NAND flash sector, where the chip prices remain volatile and suppliers require huge capital to expand their production capacity, Durcan indicated. In China, nevertheless, implementing the model could be complex since every group of investors has their own interests and values that have to be materialized, Durcan said.

In addition, Durcan commented that 2017 will be a "pretty good" year for the DRAM market as supply seems to be well-controlled and demand is strong. As for NAND flash, end-market demand is growing fast while suppliers are transitioning to 3D technologies. The NAND flash market for 2017 is more difficult to predict, Durcan said, but he believes the supply will still be tight at least for the first half of 2017.

The overall memory market outlook for the next 18 months is quite positive, said Durcan, adding that suppliers are more cautious about their investments and capacity expansions. At least spending from Micron's competitors tends to be more reasonable, Durcan said.

In other news, Micron on December 12 celebrated the completion of its share swap agreement with Inotera. Leaders from both companies joined Taiwan President Tsai Ing-wen for a closing ceremony at Inotera's headquarters in Taoyuan. Durcan remarked at the ceremony that the company will continue to expand its investment in Taiwan with plans to establish a backend facility in Taichung for the manufacture of 3D DRAM products, and to add more than 1,000 jobs at its local sites over a number of years.

http://www.digitimes.com/news/a20161214PD200.html

Cooperation for Global Competition LG and Samsung Groups’ Interdependence Likely to be Rising

Samsung Group and LG Group are working more and more closely with each other in the IT and consumer electronics industries. For example, Samsung Electronics is discussing the supply of smartphone batteries with LG Chem after the discontinuation of the Galaxy Note 7 attributable to battery explosion. LG Electronics smartphones such as the G5 are adopting DRAM and NAND flash chips manufactured by Samsung Electronics, too. LG Innotek recently began to supply 2 metal chip-on films, a smartphone component, to Samsung Electronics.
Industry insiders are regarding their cooperation as an essential element for the growth of those sectors. Until 2010 or so, both groups were running the same businesses, such as TV, mobile phone, consumer electronics and display, except for semiconductor. Their business strategies began to show some difference with the advent of smartphones and now they have reached a point where they are required to be complementary to each other.
These days, the LG Group is focusing on automotive electronics and expanding the business via LG Electronics, LG Chem and LG Innotek. LG Display is planning to manufacture automotive OLED panels from late next year as well. The Samsung Group is showing few noticeable movements in this industry.
They are moving in different directions in the TV market, too. LG is increasing its large OLED panel manufacturing facilities whereas Samsung is concentrating on quantum dot display. “Each of the two will have to procure components and materials it does not produce with the help of the other more and more frequently down the road,” said an industry source.


http://www.businesskorea.co.kr/english/news/ict/16765-cooperation-global-competition-lg-and-samsung-groups%E2%80%99-interdependence-likely-be

Seagate, SK Hynix said to team up for enterprise SSDs

Seagate and SK Hynix will form a joint venture dedicated to developing SSDs for enterprise servers and data centers, according to industry sources.

The joint venture will combine Seagate's expertise in hard disk drives with SK Hynix' complete embedded flash and SSD solutions to create a new player in the enterprise SSD market, which is currently dominated by Samsung and Intel, said the sources.

Western Digital earlier in 2016 completed its acquisition of SanDisk making the pair the first camp consolidating their respective areas of expertise, Western Digital's in HDD and SanDisk in SSD, the sources noted. Seagate and SK Hynix are expected to follow suit by forming a joint venture.

SK Hynix previously acquired California-based Link_A_Media Devices (LAMD), a developer of memory-chip controllers, which has already improved its competitiveness in the SSD field by releasing products equipped with its in-house developed controller chips, the sources identified. SK Hynix plans to have its controller design team consolidated into the new company, while Seagate will transfer part of its technical team to the entity, the sources said.

In other news, Silicon Motion Technology has entered the supply chain of the Alibaba Group by providing the e-commerce company SSD solutions, the sources noted. Silicon Motion previously acquired Shannon Systems, a China-based supplier of enterprise-class PCIe SSD and storage array solutions, which is helping the memory controller device supplier expand its presence in China, the sources said.

http://www.digitimes.com/news/a20161213PD206.html

Lattice gives iCE40 more power, I/O and memory

The new devices, dubbed UltraPlus, have more memory (1.1 Mbit RAM), twice the digital signal processors (8x DSPs), and improved I/Os over previous generations.

Typically they are used for application specific processing offload in battery-powered systems. These applications include: voice recognition, gesture recognition, image recognition, haptic and graphics acceleration.
According to Lattice: “More DSPs offer the ability to compute higher- quality algorithms, while increased memory allows data to be buffered for longer low-power states. The flexible I/Os enable a more distributed heterogeneous processing architecture.”
Product features include:

• 1.1 Mbit SRAM, 8 DSP blocks, up to 5K LUTs and non-volatile configuration
• MIPI-I3C support for low-resolution, always-on camera applications
• Sub 100uW standby power consumption
• Package size as small as 2.15 x 2.55mm

“The iCE40 UltraPlus FPGAs expand its market reach to system designers who require FPGA functionality with improved DSP compute power, more I/Os and increased memory for buffering,” said C.H. Chee, senior director of marketing, mobile & consumer division at Lattice Semiconductor.

The iCE40 UltraPlus product evaluation samples and boards are available immediately. More details can be found at www.latticesemi.com/iCE40UltraFamily.


http://www.electronicsweekly.com/news/lattice-gives-ice40-power-io-memory-2016-12/

Graphene transistors could make electronic bioprobes

Researchers at Harvard University in the US have made novel biosensors from graphene transistors that work in high-ionic-strength solutions typical of biological systems. The devices could be used to analyse blood and body fluids in real time, and analyse proteins, nucleic acids and other molecules without the need for target fluorescent labelling. They might even be exploited in implantable electronic probes such as those that detect critical neurotransmitter signals within the brain.

Nanoscale field-effect transistor (FET) sensors could be ideal for label-free real-time detection of biomolecules, but they also have, what many researchers thought, an insurmountable limitation, explains team leader Charles Lieber. “This was that they could not be used in physiological conditions because the high ionic strength would produce a short Debye length, thus screening the charge that we wish to detect. Previous work (including that by our group) tried to overcome this problem by reducing the ionic strength of the solutions used, but this means that we can cannot detect biological molecules in their real environment.”
Lieber and colleagues have now found a way around this problem by extending a concept they recently reported for nanowire FET devices in which graphene FET sensors are modified with a biomolecule-permeable polymer layer made from polyethylene glycol (or PEG) and spacer molecules, or PEG and analyte-specific DNA-aptamer receptors. “The polymer layer increases the effective Debye screening length near the FET surface and thus allows us to directly detect molecules in high-ionic-strength solutions in real time,” says Lieber.

A multi-use selective biosensor

“We showed that PEG-coated graphene FETs in physiological concentrations (100 mM buffer solution) can reversibly detect a molecule known as prostate specific antigen (PSA) at concentrations from 1 to 1000 nM,” he tells nanotechweb.org. “In contrast, similar FETs without PEG functionalization can only detect PSA in buffer salt concentrations lower than 50 nM.”
“Another important result is that when we co-modified graphene devices with PEG and aptamers yielding specific binding and detection of PSA at physiological pH, these devices showed high selectivity against other proteins,” he adds. “We also demonstrated that the PEG/aptamer-modified biosensor can be regenerated so that it can be applied as a multi-use selective biosensor under physiological conditions.”

Devices made using standard photolithography

The researchers made their graphene transistors using standard photolithography in several key steps. First, graphene grown by chemical vapour deposition was transferred onto a silicon device fabrication wafer. Next, the graphene FET channels were defined by photolithography and oxygen plasma etching. Finally, passivated metal source/drain contacts were fabricated through a second photolithography step.
“To detect biomolecules in physiological solutions, we selectively modified the graphene device surfaces by adsorbing pyrene butyric acid (PYCOOH) onto them,” explains Lieber. “Then, the functional carboxyl groups (COOH) were coupled to PEG and spacer molecules or PEG and aptamer receptors using 1-ethyl-3-(3-dimethylaminopropyl)carbodiimide hydrochloride (EDC) and N-hydroxysulfosuccinimide (Sulpho-NHS). The modified device chips were finally mated to a polydimethylsiloxane (PDMS) microfluidic channel on the device region for the sensing measurements.”
According to the team, reporting its work in PNAS doi: 10.1073/pnas.1625010114, there are many “exciting” applications for the devices, including truly unique clinical and point-of-care sensors that can analyse blood and body fluids directly without having to adjust the high ionic strength of these fluids. “New applications for fundamental biological studies where we can analyse proteins, nucleic acids and other species in real time without the need to fluorescently label the targets both outside and inside cells are possible,” says Lieber. “We could even apply this unique physiologically compatible non-destructive detection capability to make implantable electronics probes – such as our recently reported syringe-injectable electronics, where it could be possible not only to detect electric signals but also ones from critical neurotransmitters within the brain in real time.”
The researchers say they are now planning to incorporate their FET biosensors into free-standing nanoelectronics scaffolds to enable long-term monitoring in biological and electrical signals in engineered tissues. “We believe this could dramatically transform tissue implants in regenerative medicine,” adds Lieber.

http://nanotechweb.org/cws/article/tech/67240

ARM Offers Support For TSMC 7nm Manufacturing

LONDON--ARM Ltd. announced the availability for evaluation and licensing of its Artisan physical IP platform for the 7nm 7FF FinFET process from TSMC, as well as a design win at that level with Xilinx Inc.

The IP set does not include support for extreme ultraviolet (EUV) lithography, which is expected to be deployed later.
"The physical IP platform is available for tape outs in 1H17. We see some engineering samples in 2017," Ron Moore, vice president of marketing in the physical design group at ARM, told EE Times Europe. However, it is not clear that there is a performance, power or area benefit in selecting the 7FF process over the 10FF process.
The 10FF was a marked scaling over 16FF+ that could produce a 20 percent speed increase at the same power, or more than 40 percent power reduction at the same speed, according to past reports (see TSMC Symposium: 10nm is ready for design starts). But it came at the cost of the increased use of double patterning.
Moore explained: "Basically TSMC has two nodes that are distinctly different 16/14 and 10/7. For TSMC, 7nm is the next generation from 10nm. But there are additional challenges such as lay-out rules and the electrical properties of transistors."
You can expand that list to include process variation, routability, analysis for sign-off, timing variation and electromigration. And at 7nm without EUV there will be a requirement for triple patterning.
"We will have to redefine our cells to take account of EUV but 7FF is based on immersion lithography," said Moore.
Routability used to be about relieving the congestion of wiring. It still is but at 7nm it has to be done with special attention to voltage drop and electromigration and parasitics have made it difficult to design a power grid. ARM has a developed a power grid architect that includes knowledge of the logic libraries. ARM claims that as a result, a knowledgeable SoC designer can create a power grid that meets their needs within a matter of hours, versus the several days and iterations it may have taken previously.

However, all of the extra work does mean that an area reduction is not guaranteed.

"The transistors may be smaller, but that does not necessarily mean smaller cells," said Moore. As has been seen in the past scaling of the front-end-of-line (FEOL) does not produce an area benefit if it is hobbled by an earlier generation of back-end-of-line (BEOL). There are in effect multiple levels of optimization; transistor, standard cells, IP blocks, cores.
"Area savings can be realized at the core level but it is not a trivial task. It is about optimization for the combination of performance, power consumption and area [PPA]." For example ARM has also had to invent a memory compiler that could utilize a cell-based layout – rather than a more simplistic grid – to minimize variation. Minimizing variation leads to less design margin and better memory PPAhttp://www.eetimes.com/document.asp?_mc=RSS%5FEET%5FEDT&doc_id=1330963&page_number=2

Bluetooth Beams New Spec, Chips

SAN JOSE, Calif. — The Bluetooth Special Interest Group officially ratified its version 5, which includes a modular set of optional extensions for throughput, range, and other features. Chip makers, including Cypress and Nordic, are already sampling parts supporting the specs that do not include mesh networking, a piece delayed until mid-2017.

The specs define a new modulation scheme for throughput up to 2 Mbits/second. A new forward error correction technique can quadruple range to an estimated 120 meters, albeit at significantly lower data rates.
The specs also expand the data messages carried over Bluetooth beacons from about 30 bytes to about 256 bytes. As a result, beacons will be able to broadcast a URL rather than a unique identifier pointing to one, enabling greater ease of use.
Beacons are a much-talked-about but still nascent application, with about 8 million units shipping this year and a total of 565 million by 2012, according to ABI Research. They are used for retail advertising, automated museum docents, and even broadcasting a URL to a manual so that OEMs don’t have to print and ship one with a product.
A final mesh spec is the next big thing for Bluetooth, something individual vendors already support but won’t be formally ratified until about June. It will use a flooding approach that is simpler to implement than routing used on Zigbee and Thread.
The trade-off is that “all nodes receive information and pass it on, even when it is not relevant; this means devices spend more time awake and relaying information than is necessary, increasing the power consumption of the network,” said Andrew Zignani, an analyst at ABI.
Among its challenges, Bluetooth needs to get designed into more hubs and gateways to enable mesh and long-range links. The community also has an ongoing debate about support for IPv6 to end nodes, something that some see as critical for interoperability and that others say generates unnecessary power and memory requirements.
With Bluetooth 5 and eventually meshing, links can expand through a house or even a building without the need of device-to-device pairing.
“A Bluetooth light switch with a coin cell can last for years, and you can’t do that with Wi-Fi — there are a lot of apps that only need a small piece of data and low power and are only possible with Bluetooth,” said Mark Powell, executive director of the Bluetooth SIG.
Some 3.5 billion Bluetooth links are expected to ship this year, most of them in smartphones with the next largest group in wireless headphones and speakers. Apple’s decision to end support of headphone jacks in the iPhone is expected to drive wireless headsets to volumes greater than wired versions.
The smart home is Bluetooth's biggest growth area. Its share of the smart home market is expected to rise from 8% today to more than 26% by 2021, according to ABI Research. By contrast, 802.15.4 variants including ZigBee, Thread, and 6LoWPAN will rise from just under 17% of the market today to almost 30% by 2021. 

For its part, Nordic Semiconductor is sampling its nRF52840 and Bluetooth 5 software to go with it. The chip is not slated for volume production until late next year. It also adds support for 802.15.4 radios and ARM’s CryptoCell-310 embedded security block.
The Nordic chip includes a power amp, boosting output power considerably to drive greater throughput and range. Nordic doubled flash to 1 Mbyte and quadrupled RAM to 256 Kbytes compared to its previous 55-nm part.
Similarly, Cypress is sampling a Bluetooth chip with a boosted power amp to extend range to 400 meters and data rates to 2 Mbits/s, albeit at the cost of higher power consumption. The CYW20719 complies with Bluetooth 4.2 and is “Bluetooth 5-ready.” Cypress also supports a Bluetooth mesh capability on its Bluetooth version 4.2 chips.

 http://www.eetimes.com/document.asp?doc_id=1330948

Chipmakers announce 7nm technology

As silicon chips approach physical limits, it is becoming harder and more costly to deliver each new generation of technology. Yet the foundries that fabricate most of the world's chips seem to be announcing new nodes at a faster pace as they compete to make the chips that power the latest and greatest gadgets. This week, at an industry conference known as IEDM, the foundries announced details of the first 7nm process technology.
TSMC (Taiwan Semiconductor Manufacturing Company), the world's largest contract chipmaker, announced a 7nm process with the latest version of its 3D FinFET transistors for making future processors for smartphones and other mobile devices. To demonstrate the technology, TSMC produced a fully-function 256Mb SRAM test chip with the smallest reported memory-cell size (0.027 square microns). TSMC said the 7nm process will deliver either a 40 percent boost in performance or a 65 percent reduction in power at the transistor level compared to the current 16nm FinFET process. It is also less than half the size at 0.43x transistor density.
That all sounds impressive, but it's worth pointing out that TSMC is not comparing it to 10nm--which is widely expected to be a short-lived node--so the gains here are for two process nodes (or perhaps three if rumors of an interim "12nm process" are accurate). Nevertheless, the fabrication of a fully-functional chip with good performance and reliability at "high yield" (around 50 percent for the SRAM but much lower for logic) is a notable achievement, and TSMC emphasized that it is focused on helping customers get their 7nm chips to market as quickly as possible.
The competing R&D alliance of GlobalFoundries, Samsung Electronics and IBM also announced a 7nm process technology, but it is taking a different approach. TSMC is using the current 193nm immersion lithography tools while the alliance's process relies on a new form of lithography, known as EUV or extreme ultra-violet, to pattern some critical layers. Since EUV won't be ready for volume production until 2018-2019, this process may take longer to get to market, but it could deliver better scaling and lower cost.
Indeed, the group said that its 7nm process delivered the tightest pitches ever reported for FinFET transistors. The key dimensions for the 7nm process all show true scaling over those of the 10nm process the alliance announced at VLSI Symposium in 2014. The dimensions are so small, it said, that without EUV some layers could easily require four masks, a process that not only significantly increases the cost but also results in more defects. The alliance also used high-mobility materials and novel strain techniques to improve the performance of the transistors, which it said will deliver 35 percent to 40 percent better performance.
TSMC plans to start 10nm volume production this quarter with 7nm slated for the end of 2017. Samsung has already started mass production at 10nm and the first mobile processors are likely to be announced early next year. GlobalFoundries is planning to skip 10nm altogether and go directly to 7nm. It will start "risk production" in early 2018, which means 7nm will be in volume production around one year later.

The rapid pace implies that the foundries have taken the lead in semiconductor process technology. Intel has delayed 10nm production and won't release the first processors, Cannonlake desktop chips, until late 2017. As a stopgap, Intel released a third family of 14nm processors known as Kaby Lake.
But node names are misleading since they no longer bear any relation to actual chip dimensions. It is taking longer for Intel to get to each node, but it continues to deliver true Moore's Law scaling while, in some cases, the foundries have rolled out nodes that deliver little to no physical shrink. The key dimensions for Intel's 14nm node (the distances between the fins, gates and smallest metal lines) are similar to those of the foundries' 10nm processes, and it is reasonable to assume that Intel's 10nm process will be comparable to competitors' 7nm technology.

http://www.zdnet.com/article/chipmakers-announce-7nm-technology/

Global semicon sales to grow at modest pace in 2017 and 2018

http://www.thestar.com.my/business/business-news/2016/12/06/global-semicon-sales-to-grow-at-modest-pace-in-2017-and-2018/

KUALA LUMPUR: Global semiconductor sales are expected to grow at a modest pace in all the regions in 2017 and 2018 after flat annual sales projected for this year, says the US-based Semiconductor Industry Association (SIA).

It said on Monday that a new World Semiconductor Trade Statistics (WSTS) forecast showed that global sales were expected to be US$335bil in 2016, down 0.1% from the 2015 sales.

Beyond 2016, the industry was expected to record a 3.3% growth globally for 2017 (US$346.1bil in total sales) and 2.3% growth for 2018 (US$354.0bil).

For October 2016, worldwide sales of semiconductors reached US$30.5bil, up 3.4% from the previous month’s total of US$29.5bil. The sales were 5.1% higher than October 2015’s US$29bil.

SIA president and CEO John Neuffer said the global semiconductor market has rebounded in recent months, with October marking the largest year-to-year sales increase since March 2015.

“Sales increased compared to last month across all regional markets and nearly every major semiconductor product category.

“Meanwhile, the latest industry forecast has been revised upward and now calls for flat annual sales in 2016 and small increases in 2017 and 2018. All told, the industry is well-positioned for a strong close to 2016,” he said.

In October, regionally, year-on-year sales increased in China (14%), Japan (7.2%), Asia Pacific/All Other (1.9%), and the Americas (0.1%), but decreased in Europe (-3%).

Compared with September, sales were up across all regional markets: the Americas (6.5%), China (3.2%), Japan (3.0%), Europe (2.2%), and Asia Pacific/All Other (2.0%).

The SIA also endorsed the WSTS Autumn 2016 global semiconductor sales forecast, which projects the industry’s worldwide sales will be US$335bil in 2016, a 0.1% decrease from the 2015 sales total.

WSTS projects a year-to-year increase in Japan (3.2%) and Asia Pacific (2.5%), with decreases expected in Europe (-4.9%) and the Americas (-6.5%).

Among major semiconductor product categories, WSTS forecasts growth in 2016 for sensors (22.6%), discretes (4.2%), analog (4.8%) and MOS micro ICs (2.3%), which include microprocessors and microcontrollers.

Texas Instruments CFO March to Retire after 13 Years; Controller Lizardi Next CFO

Analog chip giant Texas Instruments (TXN) this afternoon said it will name corporate controller, Rafael Lizardi, as its new chief financial officer in February, replacing 32-year veteran Kevin March, who has been CFO for thirteen years, and is retiring at age 58.
March will stay on through October of next year to “oversee the transition duties.”
Shares of TI were down a penny in late trading at $70.40.
Lizardi, age 44, joined TI in 2001 after a career as a captain in the U.S. Army Corps of Engineers, the company said.
TI CEO Rich Templeton remarked on Lizardi’s “discipline” and “integrity,” saying that his “years in finance and controller positions for our manufacturing and our analog product lines have enabled him to develop in-depth knowledge of our semiconductor operations.”
He also thanked March, saying that “customers, shareholders and employees have all been beneficiaries of Kevin’s disciplined financial management and his commitment to ensure that owners of TI shares get a good return on their investment.”
“The company’s financial systems and its balance sheet have never been stronger thanks to his oversight.”

http://blogs.barrons.com/techtraderdaily/2016/12/01/texas-instruments-cfo-march-to-retire-after-13-years-controller-lizardi-next-cfo/

Falling smartphone IC ASPs discouraging device vendors from developing chips in-house

Device vendors including Xiaomi, LG Electronics and Sony have all expressed their intention to develop smartphone chips in-house. Nevertheless, the average selling price for smartphone SoCs has been trending down, while the cost of developing advanced chips using 10nm and below process technologies is high.

Consequently, these device vendors are being discouraged from developing their own smartphone SoCs, and will be cautious about increasing adoption of in-house developed chips in their own-brand smartphones, according to market sources.

The decelerating global smartphone market is another factor discouraging those device vendors' development of chips particularly high-end ones in-house, said the sources. With the industry heading towards sub-10nm nodes, the cost of developing advanced chips is pretty high. Profits from selling devices may not be able to offset the cost paid for the effort, the sources indicated.

Meanwhile, despite being less optimistic about profits made from their in-house developed chip businesses, Apple, Samsung and Huawei are gearing up to introduce their next-generation products built using 10nm process technology in 2017, the sources noted.

The smartphone market growth has been decelerating in 2016. Among the first-tier smartphone vendors, Apple could be the only one able to maintain its usual profit growth in 2016, according to sources at Taiwan-based IC design houses. Meanwhile, China-based Oppo and Vivo will continue to improve their EPS while other brand smartphone firms will likely see their earnings shrink or even suffer losses, said the sources.

http://www.digitimes.com/news/a20161201PD204.html